module Timers (
    input PCLK,
    input PRESETn,
    input PENABLE,
    input PSEL,
    input [31:0] PADDR,
    input PWRITE,
    input [31:0] PWDATA,
    input TIMCLK,
    input TIMCLKEN1,
    input TIMCLKEN2,
    output [31:0] PRDATA,
    output TIMINT1,
    output TIMINT2,
    output TIMINTC,
    input TimerITCRwrEn,
    input 1,
    input 2,
    output data,
    output delay,
    output with
);

endmodule
